A frequency synthesizer plays a very important role in current communication systems, which may be wired or wireless receivers, mobile phones or satellite receivers. A frequency synthesizer is used for generating a periodic signal having known frequency and phase relationships with a reference signal. This generated clock signal can be used as a clock source for a processor in a high-speed data transfer interface, a sampling clock for an analog-to-digital converter, or a local oscillator signal in a radio transmitter for frequency mixing. Various frequency synthesis technologies have been proposed over years, such as phase-locked loop (PLL), direct digital frequency synthesis (DDFS), frequency mixing, and the like. In these frequency synthesis technologies, phase-locked loop offers a frequency synthesizer which has a number of performances at the same time.
A PLL is a frequency control system with a negative feedback. By sensing a phase error between the feedback path and an input reference signal, the PLL generates a signal associated with the phase error to control the output frequency of an oscillator in order to achieve constant frequency and phase relationships with the reference signal. PLLs can further be used to modulate or demodulate signals.
In general, a phase-locked loop is designed based on phase noise, jitter performance, adjustable bandwidth, power consumption, the area of a chip and etc. With the rapid progression of manufacturing processes, in low-voltage deep sub-micrometer CMOS manufacturing process, the integration density of digital circuits on a single chip is increased, and parasitic capacitance and supply voltage are reduced, such that the digital circuits have higher operating frequencies and lower power consumptions. On the contrary, analog circuits have smaller voltage tolerance, larger leakage current and noise influence under the SoC environment, so as to increase the difficulty in designing a high-performance phase-locked loop.
FIG. 1 shows the structure of a traditional non-integer PLL consisting of a phase frequency detector (PFD) 10, a charge pump 11, a loop filter 12, a voltage controlled oscillator (VCO) 13, a multi-modulus frequency divider 14, and a delta-sigma modulator (ΣΔ) 15. The bandwidth of the non-integer PLL is determined by the charge/discharge current value of the charge pump 11, the resistance and capacitance of the loop filter 12, and the gain of the VCO 13. Unfortunately, the above parameters are influenced by process variations, resulting in deviations of the actual circuit characteristics from the original design values, and hindering the achievement of best noise bandwidth. Also, the multi-modulus frequency divider needs to be redesigned for different manufacturing processes. This is not only time consuming, but also results in more power consumption.
Therefore, it is an urgent need to develop a method that is capable of self-calibrating the bandwidth of a phase-locked loop and a method for measuring the output noise signal of the phase-locked loop.